View MC145170_193288.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC145170-1/D
MC145170-1
Advance Information PLL Frequency Synthesizer with Serial Interface
CMOS
The new MC145170-1 is pin-for-pin compatible with the MC145170. A comparison of the two parts is shown in the table below. The MC145170-1 is recommended for new designs. The MC145170-1 is a single-chip synthesizer capable of direct usage in the MF, HF, and VHF bands. A special architecture makes this PLL the easiest to program in the industry. Either a bit- or byte-oriented format may be used. Due to the patented BitGrabberTM registers, no address/steering bits are required for random access of the three registers. Thus, tuning can be accomplished via a 2-byte serial transfer to the 16-bit N register. The device features fully programmable R and N counters, an amplifier at the fin pin, on-chip support of an external crystal, a programmable reference output, and both single- and double-ended phase detectors with linear transfer functions (no dead zones). A configuration (C) register allows the part to be configured to meet various applications. A patented feature allows the C register to shut off unused outputs, thereby minimizing noise and interference. In order to reduce lock times and prevent erroneous data from being loaded into the counters, a patented jam-load feature is included. Whenever a new divide ratio is loaded into the N register, both the N and R counters are jam-loaded with their respective values and begin counting down together. The phase detectors are also initialized during the jam load. * Operating Voltage Range: 2.5 to 5.5 V * Maximum Operating Frequency: 185 MHz @ Vin = 500 mV p-p, 4.5 V Minimum Supply 100 MHz @ Vin = 500 mV p-p, 3.0 V Minimum Supply * Operating Supply Current: 0.6 mA @ 3 V, 30 MHz 1.5 mA @ 3 V, 100 MHz 3.0 mA @ 5 V, 50 MHz 5.8 mA @ 5 V, 185 MHz * Operating Temperature Range: - 40 to 85C * R Counter Division Range: 1 and 5 to 32,767 * N Counter Division Range: 40 to 65,535 * Direct Interface to Motorola SPI and National MICROWIRETM Serial Data Ports * Chip Complexity: 4800 FETs or 1200 Equivalent Gates * See Application Note AN1207/D COMPARISION OF THE PLL FREQUENCY SYNTHESIZERS
Parameter Technology Maximum Frequency with 5 V 10% Supply, fin Maximum Frequency with 5 V 10% Supply, OSCin Maximum Supply Voltage Maximum Input Capacitance, fin MC145170-1 1.2 m CMOS 185 MHz 25 MHz 5.5 V 7 pF MC145170 1.5 m CMOS 160 MHz 20 MHz 6.0 V 5 pF
P SUFFIX PLASTIC DIP CASE 648
16 1
16 1
D SUFFIX SOG PACKAGE CASE 751B
16 1
DT SUFFIX TSSOP CASE 948C
ORDERING INFORMATION
MC145170P1 Plastic DIP MC145170D1 SOG Package MC145170DT1 TSSOP
PIN ASSIGNMENT
OSCin OSCout REFout fin Din ENB CLK Dout 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD V R PDout VSS LD fV fR
This document contains information on a new product. Specifications and information herein are subject to change without notice.
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 1 3/96
(c) Motorola, Inc. 1996 MOTOROLA
MC145170-1 1
BLOCK DIAGRAM
OSCin OSCout 1 2 OSC 15-STAGE R COUNTER fR CONTROL 9 fR
15 REFout 3 4-STAGE REFERENCE DIVIDER BitGrabber R REGISTER 15 BITS
3
LOCK DETECTOR AND CONTROL
11
LD
CLK Din Dout 6
7 5 SHIFT REGISTER AND CONTROL LOGIC BitGrabber C REGISTER 8 BITS
16
PHASE/FREQUENCY DETECTOR A AND CONTROL
13 PDout
8
POR ENB PHASE/FREQUENCY DETECTOR B AND CONTROL BitGrabber N REGISTER 16 BITS 16 fin 4 10 14 15 R V
fV CONTROL PIN 16 = VDD PIN 12 = VSS
fV
INPUT AMP
16-STAGE N COUNTER
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Vin Vout Iin Iout IDD PD Tstg TL Parameter DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VDD and VSS Pins Power Dissipation, per Package Storage Temperature Lead Temperature, 1 mm from Case for 10 seconds Value - 0.5 to + 5.5 - 0.5 to VDD + 0.5 - 0.5 to VDD + 0.5 10 20 30 300 - 65 to + 150 260 Unit V V V mA mA mA mW C C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
MC145170-1 2
MOTOROLA
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA = - 40 to + 85C)
Symbol VDD VIL Parameter Power Supply Voltage Range Maximum Low-Level Input Voltage* (Din, CLK, ENB, fin) Minimum High-Level Input Voltage* (Din, CLK, ENB, fin) Minimum Hysteresis Voltage (CLK, ENB) Maximum Low-Level Output Voltage (Any Output) Minimum High-Level Output Voltage (Any Output) Minimum Low-Level Output Current (PDout, REFout, fR, fV, LD, R, V) Minimum High-Level Output Current (PDout, REFout, fR, fV, LD, R, V) Minimum Low-Level Output Current (Dout) Minimum High-Level Output Current (Dout) Maximum Input Leakage Current (Din, CLK, ENB, OSCin) Maximum Input Current (fin) Maximum Output Leakage Current (PDout) (Dout) IDD Idd Maximum Quiescent Supply Current Maximum Operating Supply Current Vin = VDD or VSS; Outputs Open; Excluding fin Amp Input Current Component fin = 500 mV p-p; OSCin = 1 MHz @ 1 V p-p; LD, fR, fV, REFout = Inactive and No Connect; OSCout, V, R, PDout = No Connect; Din, ENB, CLK = VDD or VSS Iout = 20 A Iout = - 20 A Vout = 0.3 V Vout = 0.4 V Vout = 0.5 V Vout = 2.2 V Vout = 4.1 V Vout = 5.0 V Vout = 0.4 V Vout = 4.1 V Vin = VDD or VSS Vin = VDD or VSS Vin = VDD or VSS, Output in High-Impedance State dc Coupling to fin Test Condition VDD V -- 2.5 4.5 5.5 2.5 4.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 4.5 4.5 5.5 5.5 5.5 5.5 5.5 -- Guaranteed Limit 2.5 to 5.5 0.50 1.35 1.65 2.00 3.15 3.85 0.15 0.20 0.1 0.1 2.4 5.4 0.12 0.36 0.36 - 0.12 - 0.36 - 0.36 1.6 - 1.6 1.0 120 100 5 100 ** Unit V V
VIH
dc Coupling to fin
V
VHys VOL VOH IOL
V V V mA
IOH
mA
IOL IOH Iin Iin IOZ
mA mA A A nA A A mA
* When dc coupling to the OSCin pin is used, the pin must be driven rail-to-rail. In this case, OSCout should be floated. ** The nominal values at 3 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5 V are 3.0 mA @ 50 MHz, and 5.8 mA @ 185 MHz. These are not guaranteed limits.
MOTOROLA
MC145170-1 3
AC INTERFACE CHARACTERISTICS ( TA = - 40 to + 85C, CL = 50 pF, Input tr = tf = 10 ns unless otherwise indicated)
Symbol fclk Parameter Serial Data Clock Frequency (Note: Refer to Clock tw Below) Figure No. 1 VDD V 2.5 4.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 -- -- Guaranteed Limit dc to 3.0 dc to 4.0 dc to 4.0 150 85 85 300 200 200 0 to 200 0 to 100 0 to 100 150 50 50 900 150 150 10 10 Unit MHz
tPLH, tPHL
Maximum Propagation Delay, CLK to Dout
1, 5
ns
tPLZ, tPHZ
Maximum Disable Time, Dout Active to High Impedance
2, 6
ns
tPZL, tPZH
Access Time, Dout High Impedance to Active
2, 6
ns
tTLH, tTHL
Maximum Output Transition Time, Dout
CL = 50 pF
1, 5
ns
CL = 200 pF
1, 5
ns
Cin Cout
Maximum Input Capacitance - Din, ENB, CLK Maximum Output Capacitance - Dout
pF pF
TIMING REQUIREMENTS ( TA = - 40 to + 85C, Input tr = tf = 10 ns unless otherwise indicated)
Symbol tsu, th Parameter Minimum Setup and Hold Times, Din vs CLK Figure No. 3 VDD V 2.5 4.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 Guaranteed Limit 55 40 40 135 100 100 400 300 300 166 125 125 100 100 100 Unit ns
tsu, th, trec
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
4
ns
tw(H)
Minimum Inactive-High Pulse Width, ENB
4
ns
tw
Minimum Pulse Width, CLK
1
ns
tr, tf
Maximum Input Rise and Fall Times, CLK
1
s
MC145170-1 4
MOTOROLA
SWITCHING WAVEFORMS
tf 90% CLK 50% 10% tw 1/fclk tPLH Dout 90% 50% 10% tTLH tTHL tPHL tPZH Dout 50% tPHZ 90% VSS HIGH IMPEDANCE tw Dout tr VDD VSS ENB 50% tPZL 50% VDD VSS tPLZ 10% HIGH IMPEDANCE VDD
Figure 1.
Figure 2.
tw(H) VALID VDD Din 50% VSS tsu CLK th 50% VSS VDD tsu CLK th trec VDD 50% FIRST CLK LAST CLK VSS ENB 50% VSS VDD
Figure 3.
Figure 4.
TEST POINT
TEST POINT 7.5 k
DEVICE UNDER TEST
CL *
DEVICE UNDER TEST
CL *
CONNECT TO VDD WHEN TESTING tPLZ AND tPZL. CONNECT TO VSS WHEN TESTING tPHZ AND tPZH.
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
Figure 5. Test Circuit
Figure 6. Test Circuit
MOTOROLA
MC145170-1 5
LOOP SPECIFICATIONS ( TA = - 40 to + 85C)
Symbol f Parameter Input Frequency, fin Test Condition Vin 500 mV p-p Sine Wave, N Counter Set to Divide Ratio Such that fV 2 MHz Vin 1 V p-p Sine Wave, OSCout = No Connect, R Counter Set to Divide Ratio Such that fR 2 MHz C1 30 pF C2 30 pF Includes Stray Capacitance CL = 30 pF Figure No. 7 VDD V 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 2.5 4.5 5.5 2.5 4.5 5.5 fR in Phase with fV CL = 50 pF CL = 50 pF 11, 12 2.5 4.5 5.5 2.5 4.5 5.5 Guaranteed Range Min 5* 5* 25* 45* 1* 1* 1* 1* 2 2 2 2 dc dc dc dc dc dc TBD 20 16 -- -- -- Max TBD 100 185 185 12 14 25 25 12 12 15 15 TBD 10 10 TBD 2 2 TBD 100 90 TBD 65 60 Unit MHz
f
Input Frequency, OSCin Externally Driven with ac-Coupled Signal Crystal Frequency, OSCin and OSCout
8
MHz
fXTAL
9
MHz
fout
Output Frequency, REFout
10, 12
MHz
f
Operating Frequency of the Phase Detectors Output Pulse Width, R, V, and LD
MHz
tw
ns
tTLH, tTHL Cin
Output Transition Times, R, V, LD, fR, and fV Input Capacitance
11, 12
ns
fin -- -- -- 7 pF OSCin -- -- -- 7 * If lower frequency is desired, use wave shaping or higher amplitude sinusoidal signal in ac-coupled case. Also, see Figure 22 for dc decoupling.
MC145170-1 6
MOTOROLA
SINE WAVE GENERATOR
100 pF fin Vin 50 * VSS VDD fV
TEST POINT
SINE WAVE GENERATOR
0.01 F OSCin 10 M Vin 50 MC145170-1 OSCout VSS VDD V+ fR
TEST POINT
MC145170-1
V+
* Characteristic impedance
Figure 7. Test Circuit
Figure 8. Test Circuit
OSCin C1 MC145170-1 REFout C2 OSCout VSS VDD TEST POINT V+ REFout 50%
1/f REFout
Figure 9. Test Circuit
Figure 10. Switching Waveform
TEST POINT OUTPUT tw OUTPUT 50% 90% 10% tTHL tTLH DEVICE UNDER TEST CL * * Includes all probe and fixture capacitance.
Figure 11. Switching Waveform
Figure 12. Test Circuit
MOTOROLA
MC145170-1 7
PIN DESCRIPTIONS
DIGITAL INTERFACE PINS Din Serial Data Input (Pin 5) The bit stream begins with the most significant bit (MSB) and is shifted in on the low-to-high transition of CLK. The bit pattern is 1 byte (8 bits) long to access the C or configuration register, 2 bytes (16 bits) to access the N register, or 3 bytes (24 bits) to access the R register. Additionally, the R register can be accessed with a 15-bit transfer (see Table 1). An optional pattern which resets the device is shown in Figure 13. The values in the C, N, and R registers do not change during shifting because the transfer of data to the registers is controlled by ENB. The bit stream needs neither address nor steering bits due to the innovative BitGrabber registers. Therefore, all bits in the stream are available to be data for the three registers. Random access of any register is provided (i.e., the registers may be accessed in any sequence). Data is retained in the registers over a supply range of 2.5 to 5.5 V. The formats are shown in Figures 13, 14, 15, and 16. Din typically switches near 50% of VDD to maximize noise immunity. This input can be directly interfaced to CMOS devices with outputs guaranteed to switch near rail-to-rail. When interfacing to NMOS or TTL devices, either a level shifter (MC74HC14A, MC14504B) or pull-up resistor of 1 to 10 k must be used. Parameters to consider when sizing the resistor are worst-case IOL of the driving device, maximum tolerable power consumption, and maximum data rate. Table 1. Register Access
(MSBs are shifted in first, C0, N0, and R0 are the LSBs) Number of Clocks 4+5 8 16 15 or 24 Other Values 32 Values > 32 Accessed Register (Reset) C Register N Register R Register None See Figures 24 -- 31 Bit Nomenclature C7, C6, C5, . . ., C0 N15, N14, N13, . . ., N0 R14, R13, R12, . . ., R0
NOTE To guarantee proper operation of the power-on reset (POR) circuit, the CLK pin must be held at the potential of either the VSS or VDD pin during power up. That is, the CLK input should not be floated or toggled while the VDD pin is ramping from 0 to at least 2.5 V. If control of the CLK pin is not practical during power up, the initialization sequence shown in Figure 13 must be used. ENB Active-Low Enable Input (Pin 6) This pin is used to activate the serial interface to allow the transfer of data to/from the device. When ENB is in an inactive high state, shifting is inhibited, Dout is forced to the high- impedance state, and the port is held in the initialized state. To transfer data to the device, ENB (which must start inactive high) is taken low, a serial transfer is made via Din and CLK, and ENB is taken back high. The low-to-high transition on ENB transfers data to the C, N, or R register depending on the data stream length per Table 1. NOTE Transitions on ENB must not be attempted while CLK is high. This puts the device out of synchronization with the microcontroller. Resynchronization occurs when ENB is high and CLK is low. This input is also Schmitt-triggered and switches near 50% of VDD, thereby minimizing the chance of loading erroneous data into the registers. See the last paragraph of Din for more information. Dout Three-State Serial Data Output (Pin 8) Data is transferred out of the 16-1/2-stage shift register through Dout on the high-to-low transition of CLK. This output is a No Connect, unless used in one of the manners discussed below. Dout could be fed back to an MCU/MPU to perform a wrap- around test of serial data. This could be part of a system check conducted at power up to test the integrity of the system's processor, PC board traces, solder joints, etc. The pin could be monitored at an in-line QA test during board manufacturing. Finally, D out facilitates troubleshooting a system and permits cascading devices. REFERENCE PINS OSCin /OSCout Reference Oscillator Input/Output (Pins 1, 2) These pins form a reference oscillator when connected to terminals of an external parallel-resonant crystal. Frequency-setting capacitors of appropriate values as recommended by the crystal supplier are connected from each pin to ground (up to a maximum of 30 pF each, including stray capacitance). An external feedback resistor of 1 to 15 M is connected directly across the pins to ensure linear operation of the amplifier. The required connections for the components are shown in Figure 9.
CLK Serial Data Clock Input (Pin 7) Low-to-high transitions on Clock shift bits available at Din, while high-to-low transitions shift bits from Dout. The chip's 16-1/2-stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. Four clock cycles followed by five clock cycles are needed to reset the device; this is optional. Eight clock cycles are required to access the C register. Sixteen clock cycles are needed for the N register. Either 15 or 24 cycles can be used to access the R register (see Table 1 and Figures 13, 14, 15, and 16). For cascaded devices, see Figures 24 -- 31. CLK typically switches near 50% of V DD and has a Schmitt-triggered input buffer. Slow CLK rise and fall times are allowed. See the last paragraph of Din for more information.
MC145170-1 8
MOTOROLA
If desired, an external clock source can be ac coupled to OSCin. A 0.01 F coupling capacitor is used for measurement purposes and is the minimum size recommended for applications. An external feedback resistor of approximately 10 M is required across the OSC in and OSC out pins in the ac-coupled case (see Figure 8). OSCout is an internal node on the device and should not be used to drive any loads (i.e., OSC out is unbuffered). However, the buffered REF out is available to drive external loads. The external signal level must be at least 1 V p-p; the maximum frequencies are given in the Loop Specifications table. These maximum frequencies apply for R Counter divide ratios as indicated in the table. For very small ratios, the maximum frequency is limited to the divide ratio times 2 MHz. (Reason: the phase/frequency detectors are limited to a maximum input frequency of 2 MHz.) If an external source is available which swings rail-to-rail (VDD to VSS), then dc coupling can be used. In the dc- coupled case, no external feedback resistor is needed. OSCout must be a No Connect to avoid loading an internal node on the device, as noted above. For frequencies below 1 MHz, dc coupling must be used. The R counter is a static counter and may be operated down to dc. However, wave shaping by a CMOS buffer may be required to ensure fast rise and fall times into the OSCin pin. See Figure 22. Each rising edge on the OSCin pin causes the R counter to decrement by one. REFout Reference Frequency Output (Pin 3) This output is the buffered output of the crystal-generated reference frequency or externally provided reference source. This output may be enabled, disabled, or scaled via bits in the C register (see Figure 14). REF out can be used to drive a microprocessor clock input, thereby saving a crystal. Upon power up, the on-chip power-on-initialize circuit forces REF out to the OSC in divided-by-8 mode. REFout is capable of operation to 10 MHz; see the Loop Specifications table. Therefore, divide values for the reference divider are restricted to two or higher for OSCin frequencies above 10 MHz. If unused, the pin should be floated and should be disabled via the C register to minimize dynamic power consumption and electromagnetic interference (EMI). COUNTER OUTPUT PINS fR R Counter Output (Pin 9) This signal is the buffered output of the 15-stage R counter. fR can be enabled or disabled via the C register (patented). The output is disabled (static low logic level) upon power up. If unused, the output should be left disabled and unconnected to minimize interference with external circuitry. The fR signal can be used to verify the R counter's divide ratio. This ratio extends from 5 to 32,767 and is determined by the binary value loaded into the R register. Also, direct access to the phase detector via the OSCin pin is allowed by choosing a divide value of 1 (see Figure 15). The maximum frequency which the phase detectors operate is 2 MHz. Therefore, the frequency of fR must not exceed 2 MHz. When activated, the fR signal appears as normally low and pulses high.
fV N Counter Output (Pin 10) This signal is the buffered output of the 16-stage N counter. fV can be enabled or disabled via the C register (patented). The output is disabled (static low logic level) upon power up. If unused, the output should be left disabled and unconnected to minimize interference with external circuitry. The fV signal can be used to verify the N counter's divide ratio. This ratio extends from 40 to 65,535 and is determined by the binary value loaded into the N register. The maximum frequency which the phase detectors operate is 2 MHz. Therefore, the frequency of fV must not exceed 2 MHz. When activated, the fV signal appears as normally low and pulses high. LOOP PINS fin Frequency Input (Pin 4) This pin is a frequency input from the VCO. This pin feeds the on-chip amplifier which drives the N counter. This signal is normally sourced from an external voltage-controlled oscillator (VCO), and is ac-coupled into fin. A 100 pF coupling capacitor is used for measurement purposes and is the minimum size recommended for applications (see Figure 7). The frequency capability of this input is dependent on the supply voltage as listed in the Loop Specifications table. For small divide ratios, the maximum frequency is limited to the divide ratio times 2 MHz. (Reason: the phase/frequency detectors are limited to a maximum frequency of 2 MHz.) For signals which swing from at least the VIL to VIH levels listed in the Electrical Characteristics table, dc coupling may be used. Also, for low frequency signals (less than the minimum frequencies shown in the Loop Specifications table), dc coupling is a requirement. The N counter is a static counter and may be operated down to dc. However, wave shaping by a CMOS buffer may be required to ensure fast rise and fall times into the fin pin. See Figure 22. Each rising edge on the fin pin causes the N counter to decrement by 1. PDout Single-Ended Phase/Frequency Detector Output (Pin 13) This is a three-state output for use as a loop error signal when combined with an external low-pass filter. Through use of a Motorola patented technique, the detector's dead zone has been eliminated. Therefore, the phase/frequency detector is characterized by a linear transfer function. The operation of the phase/frequency detector is described below and is shown in Figure 17. POL bit (C7) in the C register = low (see Figure 14) Frequency of fV > fR or Phase of fV Leading f R: negative pulses from high impedance Frequency of fV < fR or Phase of fV Lagging fR: positive pulses from high impedance Frequency and Phase of fV = fR: essentially high-impe- dance state; voltage at pin determined by loop filter POL bit (C7) = high Frequency of fV > fR or Phase of fV Leading fR: positive pulses from high impedance Frequency of fV < fR or Phase of fV Lagging f R: negative pulses from high impedance Frequency and Phase of fV = fR: essentially high-impe- dance state; voltage at pin determined by loop filter
MOTOROLA
MC145170-1 9
This output can be enabled, disabled, and inverted via the C register. If desired, PDout can be forced to the high-impe- dance state by utilization of the disable feature in the C register (patented). R and V Double-Ended Phase/Frequency Detector Outputs (Pins 14, 15) These outputs can be combined externally to generate a loop error signal. Through use of a Motorola patented technique, the detector's dead zone has been eliminated. Therefore, the phase/frequency detector is characterized by a linear transfer function. The operation of the phase/frequency detector is described below and is shown in Figure 17. POL bit (C7) in the C register = low (see Figure 14) Frequency of fV > fR or Phase of fV Leading fR: V = negative pulses, R = essentially high Frequency of fV < fR or Phase of fV Lagging fR: V = essentially high, R = negative pulses Frequency and Phase of fV = fR: V and R remain essentially high, except for a small minimum time period when both pulse low in phase POL bit (C7) = high Frequency of fV > fR or Phase of fV Leading fR: R = negative pulses, V = essentially high Frequency of fV < fR or Phase of fV Lagging fR: R = essentially high, V = negative pulses Frequency and Phase of fV = fR: V and R remain essentially high, except for a small minimum time period when both pulse low in phase
These outputs can be enabled, disabled, and interchanged via the C register (patented). LD Lock Detector Output (Pin 11) This output is essentially at a high level with narrow low- going pulses when the loop is locked (fR and fV of the same phase and frequency). The output pulses low when fV and fR are out of phase or different frequencies (see Figure 17). This output can be enabled and disabled via the C register (patented). Upon power up, on-chip initialization circuitry disables LD to a static low logic level to prevent a false "lock" signal. If unused, LD should be disabled and left open. POWER SUPPLY VDD Most Positive Supply Potential (Pin 16) This pin may range from + 2.5 to 5.5 V with respect to VSS. For optimum performance, VDD should be bypassed to VSS using low-inductance capacitor(s) mounted very close to the device. Lead lengths on the capacitor(s) should be minimized. (The very fast switching speed of the device causes current spikes on the power leads.) VSS Most Negative Supply Potential (Pin 12) This pin is usually ground. For measurement purposes, the VSS pin is tied to a ground plane.
POWER UP
ENB
CLK
1
2
3
4
1
2
3
4
5
Din ZEROES DON'T CARES ZEROES ONE ZERO DON'T CARES
NOTE: This initialization sequence must be used immediately after power up if control of the CLK pin is not possible. That is, if CLK (pin 7) toggles or floats upon power up, use the above sequence to reset the device. Also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is reduced to below 2.5 V, but not down to 0 V (for example, the supply drops down to 1 V). This is necessary because the on-chip power-on reset is only activated when the supply ramps up from 0 V.
Figure 13. Reset Sequence
MC145170-1 10
MOTOROLA
ENB
CLK
1
2
3
4
5
6
7
8
*
MSB Din C7 C6 C5 C4 C3 C2 C1
LSB C0
* At this point, the new byte is transferred to the C register and stored. No other registers are affected. C7 -- POL: Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PDout and interchanges the R function with V as depicted in Figure 17. Also see the phase detector output pin descriptions for more information. This bit is cleared low at power up. Selects which phase/frequency detector is to be used. When set high, enables the output of phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing R and V to the static high state. When cleared low, phase/frequency detector B is enabled (R and V) and phase/frequency detector A is disabled with PDout forced to the high-impedance state. This bit is cleared low at power up. Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced to a static low level. This bit is cleared low at power up.
C6 -- PDA/B:
C5 -- LDE:
C4 - C2, OSC2 - OSC0: Reference output controls which determine the REFout characteristics as shown below. Upon power up, the bits are initialized such that OSCin /8 is selected.
C4 0 0 0 0 1 1 1 1
C3 0 0 1 1 0 0 1 1
C2 0 1 0 1 0 1 0 1
REFout Frequency dc (Static Low) OSCin OSCin /2 OSCin /4 OSCin /8 OSCin /16 OSCin /8 OSCin /16
C1 -- fVE:
Enables the fV output when set high. When cleared low, the fV output is forced to a static low level. The bit is cleared low upon power up. Enables the fR output when set high. When cleared low, the fR output is forced to a static low level. The bit is cleared low upon power up.
C0 -- fRE:
Figure 14. C Register Access and Format (8 Clock Cycles are Used)
MOTOROLA
MC145170-1 11
ENB
*
Figure 15. R Register Access and Formats (Either 24 or 15 Clock Cycles Can Be Used)
MOTOROLA
OCTAL VALUE
* At this point, the new data is transferred to the R register and stored. No other registers are affected.
CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
Din R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0 0 0 0 0 0 0 0 . . . 7 7 0 0 0 0 0 0 0 0 . . . F F 0 0 0 0 0 0 0 0 . . . F F 0 1 2 3 4 5 6 7 . . . E F NOT ALLOWED R COUNTER = /1 (DIRECT ACCESS TO REFERENCE SIDE OF PHASE/FREQUENCY DETECTOR) NOT ALLOWED NOT ALLOWED NOT ALLOWED R COUNTER = /5 R COUNTER = /6 R COUNTER = /7 R COUNTER = /32,766 R COUNTER = /32,767 HEXADECIMAL VALUE DECIMAL EQUIVALENT
CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
X X X X X X X R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 DON'T CARE BITS SEE BELOW SEE BELOW SEE BELOW SEE BELOW ENB
MC145170-1 12
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 LSB 24
CLK
1
MSB
Din
X
X
*
CLK MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14 LSB
15
ENB
CLK
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 LSB
*
Din
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
0 0 0 0
0 0 0 0 0 0 0

0 0 0 0
F F

0 0 0 0 0 0 0

0 0 0 0
F F

2 2 2 2 2 2 2

0 1 2 3
F F

5 6 7 8 9 A B

NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED
E F

NOT ALLOWED NOT ALLOWED NOT ALLOWED N COUNTER = N COUNTER = N COUNTER = N COUNTER =
/ / / / / /
40 41 42 43
N COUNTER = N COUNTER =
65,534 65,535 DECIMAL EQUIVALENT
HEXADECIMAL VALUE * At this point, the two new bytes are transferred to the N register and stored. No other registers are affected. In addition, the N and R counters are jam-loaded and begin counting down together.
Figure 16. N Register Access and Format (16 Clock Cycles Are Used)
fR REFERENCE OSCin / R fV FEEDBACK (fin / N) PDout R
VH VL VH VL
*
VH HIGH IMPEDANCE VL VH VL VH VL VH VL
V LD
VH = High voltage level VL = Low voltage level *At this point, when both fR and fV are in phase, both the sinking and sourcing output FETs are turned on for a very short interval. NOTE: The PDout generates error pulses during out-of-lock conditions. When locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the low-pass filter capacitor. PDout, R, and V are shown with the polarity bit (POL) = low; see Figure 14 for POL.
Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveforms
MOTOROLA
MC145170-1 13
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS The following options may be considered to provide a reference frequency to Motorola's CMOS frequency synthesizers. Use of a Hybrid Crystal Oscillator Commercially available temperature-compensated crystal oscillators (TCXOs) or crystal-controlled data clock oscillators provide very stable reference frequencies. An oscillator capable of CMOS logic levels at the output may be direct or dc coupled to OSCin. If the oscillator does not have CMOS logic levels on the outputs, capacitive or ac coupling to OSCin may be used (see Figure 8). For additional information about TCXOs and data clock oscillators, please consult the latest version of the eem Electronic Engineers Master Catalog, the Gold Book, or similar publications. Design an Off-Chip Reference The user may design an off-chip crystal oscillator using discrete transistors or ICs specifically developed for crystal oscillator applications, such as the MC12061 MECL device. The reference signal from the MECL device is ac coupled to OSCin (see Figure 18). For large amplitude signals (standard CMOS logic levels), dc coupling is used. Use of the On-Chip Oscillator Circuitry The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure 18. The crystal should be specified for a loading capacitance (CL) which does not exceed 20 pF when used at the highest operating frequencies listed in the Loop Specifications table. Larger CL values are possible for lower frequencies. Assuming R1 = 0 , the shunt load capacitance (CL) presented across the crystal can be estimated to be: CinCout C1 * C2 CL = + Ca + Cstray + Cin + Cout C1 + C2 where Cin = 5 pF (see Figure 19) Cout = 6 pF (see Figure 19) Ca = 1 pF (see Figure 19) C1 and C2 =external capacitors (see Figure 18) Cstray = the total equivalent external circuit stray capaci- tance appearing across the crystal terminals The oscillator can be "trimmed" on-frequency by making a portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and OSCout pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. Circuit stray capacitance can also be handled by adding the appropriate stray value to the values for Cin and Cout. For this approach, the term Cstray becomes 0 in the above expression for CL. Power is dissipated in the effective series resistance of the crystal, Re, in Figure 20. The maximum drive level specified
by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shift in operating frequency. R1 in Figure 18 limits the drive level. The use of R1 is not necessary in most cases. To verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output frequency at the REFout pin (OSCout is not used because loading impacts the oscillator). The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal decreases in frequency or becomes unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the oscillator start-up time is proportional to the value of R1. Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful (see Table 2).
FREQUENCY SYNTHESIZER
OSCin
Rf R1*
OSCout
C1
C2
* May be needed in certain cases. See text.
Figure 18. Pierce Crystal Oscillator Circuit
Ca OSCin Cin Cstray Cout OSCout
Figure 19. Parasitic Capacitances of the Amplifier and Cstray
RS 1 2 1
LS
CS 2
CO 1 Re Xe 2
NOTE: Values are supplied by crystal manufacturer (parallel resonant crystal).
Figure 20. Equivalent Crystal Networks
MC145170-1 14
MOTOROLA
RECOMMENDED READING Technical Note TN-24, Statek Corp. Technical Note TN-7, Statek Corp. E. Hafner, "The Piezoelectric Crystal Unit-Definitions and Method of Measurement", Proc. IEEE, Vol. 57, No. 2, Feb. 1969.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency Control", Electro-Technology, June 1969. P. J. Ottowitz, "A Guide to Crystal Selection", Electronic Design, May 1966. D. Babin, "Designing Crystal Oscillators", Machine Design, March 7, 1985. D. Babin, "Guidelines for Crystal Oscillator Design", Machine Design, April 25, 1985.
Table 2. Partial List of Crystal Manufacturers
Name United States Crystal Corp. Crystek Crystal Statek Corp. Fox Electronics Address 3605 McCart Ave., Ft. Worth, TX 76110 2351 Crystal Dr., Ft. Myers, FL 33907 512 N. Main St., Orange, CA 92668 5570 Enterprise Parkway, Ft. Myers, FL 33905 Phone (817) 921-3013 (813) 936-2109 (714) 639-7810 (813) 693-0099
NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers.
MOTOROLA
MC145170-1 15
PHASE-LOCKED LOOP -- LOW PASS FILTER DESIGN
(A)
PDout R1
VCO
n = = F(s) =
K KVCO NR1C Nn 2KKVCO 1 R1sC + 1
C
(B)
PDout R1 R2 C
VCO
n =
K KVCO NC(R1 + R2) N R2C + KKVCO
= 0.5 n
F(s) =
R2sC + 1 (R1 + R2)sC + 1
(C) R V R1 R2 C R1 - +
R2 C A VCO = n = K KVCO NCR1 nR2C 2
ASSUMING GAIN A IS VERY LARGE, THEN: F(s) = R2sC + 1 R1sC
NOTE: For (C), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from the midpoint to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network does not significantly affect n. DEFINITIONS: N = Total Division Ratio in Feedback Loop K (Phase Detector Gain) = VDD / 4 V/radian for PDout K (Phase Detector Gain) = VDD / 2 V/radian for V and R KVCO (VCO Gain) = 2fVCO VVCO
For a nominal design starting point, the user might consider a damping factor 0.7 and a natural loop frequency n (2fR/50) where fR is the frequency at the phase detector input. Larger n values result in faster loop lock times and, for similar sideband filtering, higher fR-related VCO sidebands. RECOMMENDED READING: Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley-Interscience, 1979. Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley-Interscience, 1980. Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976. Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley-Interscience, 1981. Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983. Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978. Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980. Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538-586. New York, John Wiley & Sons. Fadrhons, Jan, "Design and Analyze PLLs on a Programmable Calculator," EDN. March 5, 1980. AN535, Phase-Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970. AR254, Phase-Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design, 1987. AN1207, The MC145170 in Basic HF and VHF Oscillators, Motorola Semiconductor Products, Inc., 1992.
MC145170-1 16
MOTOROLA
VHF OUTPUT BUFFER VHF VCO LOW-PASS FILTER V+ 1 2 V+ 3 4 5 6 MCU OPTIONAL 7 8 OSCin OSCout REFout MC145170-1 fin Din ENB CLK Dout VDD V R PDout VSS LD fV fR 16 15 14 13 12 11 10 9 OPTIONAL LOOP ERROR SIGNALS (NOTE 1)
THRESHOLD DETECTOR OPTIONAL
INTEGRATOR (NOTE 4)
NOTES: 1. The R and V outputs are fed to an external combiner/loop filter. See the Phase-Locked Loop -- Low-Pass Filter Design page for additional information. The R and V outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. 2. For optimum performance, bypass the VDD pin to VSS (GND) with one or more low-inductance capacitors. 3. The R counter is programmed for a divide value = OSCin/fR. Typically, fR is the tuning resolution required for the VCO. Also, the VCO frequency divided by fR = N, where N is the divide value of the N counter. 4. May be an R-C low-pass filter.
Figure 21. Example Application
MOTOROLA
MC145170-1 17
V+
VDD A C
OSCin
OSCout
NO CONNECT
MC74HC14A B D fin
MC145170-1
VSS
NOTE: The signals at Points A and B may be low-frequency sinusoidal or square waves with slow edge rates or noisy signal edges. At Points C and D, the signals are cleaned up, have sharp edge rates, and rail-to-rail signal swings. With signals as described at Points C and D, the MC145170-1 is guaranteed to operate down to a frequency as low as dc.
Figure 22. Low Frequency Operation Using dc Coupling
MC145170-1 18
MOTOROLA
fin (PIN 4) SOG PACKAGE
1
2 3 4
Marker 1 2 3 4
Frequency (MHz) 5 100 150 185
Resistance () 2390 39.2 25.8 42.6
Reactance () - 5900 - 347 - 237 - 180
Capacitance (pF) 5.39 4.58 4.48 4.79
Figure 23. Input Impedance at fin -- Series Format (R + jX) (5 MHz to 185 MHz)
DEVICE #1 MC145170-1 Din CLK ENB Dout Din
DEVICE #2 MC145170-1 CLK ENB Dout
33 k NOTE 1 CMOS MCU OPTIONAL NOTES: 1. The 33 k resistor is needed to prevent the Din pin from floating. (The Dout pin is a three-state output.) 2. See related Figures 25, 26, and 27.
Figure 24. Cascading Two MC145170-1 Devices
MOTOROLA
MC145170-1 19
ENB
*
Figure 26. Accessing the R Registers of Two Cascaded MC145170-1 Devices
8 25 26 27 30 9 10 31 X X R14 R13 R9 R REGISTER BITS OF DEVICE #2 IN FIGURE 24
CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC
R1 R0 X R14 R11 R7 R6 R0 R REGISTER BITS OF DEVICE #1 IN FIGURE 24
Figure 25. Accessing the C Registers of Two Cascaded MC145170-1 Devices
2 7 8 9 10 15 16 17 18 23 24 25 26 31 32 33 34 39 40 X X X X X C7 C6 C0 X X X C7 C6 C0 C REGISTER BITS OF DEVICE #2 IN FIGURE 24 C REGISTER BITS OF DEVICE #1 IN FIGURE 24 39 40 41 42 44 45 48 49 50 55
ENB
CLK
D in
CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
*
56
MC145170-1 20
CLK
1
D in
X
*At this point, the new data is transferred to the C registers of both devices and stored. No other registers are affected.
1
2
X
X
MOTOROLA
*At this point, the new data is transferred to the R registers of both devices and stored. No other registers are affected.
Figure 27. Accessing the N Registers of Two Cascaded MC145170-1 Devices
CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC
X X X X N15 N8 N7 N0 N15 N8 N7 N0 N REGISTER BITS OF DEVICE #2 IN FIGURE 24 N REGISTER BITS OF DEVICE #1 IN FIGURE 24
MOTOROLA
ENB
*
CLK
1 15 16 17 23 24 25 31 32
2
8
9
10
33
39
40
41
47
48
D in
X
*At this point, the new data is transferred to the N registers of both devices and stored. No other registers are affected.
MC145170-1 21
V+ VPD
DEVICE #1 MC145170-1 Din CLK ENB
VDD
VDD VCC
DEVICE #2 NOTE 2 ENB
VPD OUTPUT A (Dout)
Dout
Din
CLK
33 k NOTE 1 CMOS MCU OPTIONAL NOTES: 1. The 33 k resistor is needed to prevent the Din pin from floating. (The Dout pin is a three-state output.) 2. This PLL Frequency Synthesizer may be a MC145190, MC145191, MC145192, MC145200, or MC145201. 3. See related Figures 29, 30, and 31.
Figure 28. Cascading Two Different Device Types
MC145170-1 22
MOTOROLA
Figure 30. Accessing the A and R Registers of Two Different Device Types
16 20 21 22 30 17 18 31 32 A23 A22 A19 A18 A9 A8 A REGISTER BITS OF DEVICE #2 IN FIGURE 28
CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
A0 X R14 R13 R9 R8 R0 R REGISTER BITS OF DEVICE #1 IN FIGURE 28
Figure 29. Accessing the C Registers of Two Different Device Types
2 7 8 9 10 15 16 17 18 23 24 25 26 31 32 33 34 39 40 X X X X C7 C6 C0 X X X C7 C6 C0 C REGISTER BITS OF DEVICE #2 IN FIGURE 28 C REGISTER BITS OF DEVICE #1 IN FIGURE 28 39 40 41 42 43 46 47 48 55
ENB
CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
*
56
MOTOROLA
ENB
*
CLK
1
D in
X
X
*At this point, the new data is transferred to the C registers of both devices and stored. No other registers are affected.
CLK
1
2
D in
X
X
MC145170-1 23
*At this point, the new data is transferred to the A register of Device #2 and R register of Device #1 and stored. No other registers are affected.
Figure 31. Accessing the R and N Registers of Two Different Device Types
CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC
X X X X R15 R8 R7 R0 N15 N8 N7 N0 R REGISTER BITS OF DEVICE #2 IN FIGURE 28 N REGISTER BITS OF DEVICE #1 IN FIGURE 28
MC145170-1 24
ENB
*
CLK
1 15 16 17 23 24 25 31 32
2
8
9
10
33
39
40
41
47
48
D in
X
*At this point, the new data is transferred to the R register of Device #2 and N register of Device #1 and stored. No other registers are affected.
MOTOROLA
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP (DUAL-IN-LINE PACKAGE) CASE 648-08 -A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
D SUFFIX SOG (SMALL-OUTLINE GULL-WING) PACKAGE CASE 751B-05
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
MOTOROLA
MC145170-1 25
DT SUFFIX TSSOP (THIN SHRUNK SMALL-OUTLINE PACKAGE) CASE 948C-03
A -P-
16x
K
REF M
0.200 (0.008)
T
16
9
L
PIN 1 IDENTIFICATION 1 8
B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -U-. MILLIMETERS MIN MAX --- 5.10 4.30 4.50 --- 1.20 0.05 0.25 0.45 0.55 0.65 BSC 0.22 0.23 0.09 0.24 0.09 0.18 0.16 0.32 0.16 0.26 6.30 6.50 0 10 INCHES MIN MAX --- 0.200 0.169 0.177 --- 0047 0.002 0.010 0.018 0.022 0.026 BSC 0.009 0.010 0.004 0.009 0.004 0.007 0.006 0.013 0.006 0.010 0.248 0.256 0 10
C 0.100 (0.004) -TSEATING PLANE M
-UH
D
G
K J1 J A SECTION A-A K1
A M
DIM A B C D F G H J J1 K K1 L M
F
MC145170-1 26
MOTOROLA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MOTOROLA
*MC145170-1/D*
MC145170-1/D MC145170-1 27

▲Up To Search▲

Price & Availability of MC145170

	To Download MC145170 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .